Free Active Peak Detector & Hold Capacitor Tool
Size holding capacitors ($C_{hold}$) for precision active peak detectors. Balance pulse charging acquisition time against reverse diode leakage droop rate ($dV/dt = I_{leak} / C_{hold}$).
⚡ Signal Dynamics & Op-Amp Specs
📊 Sizing & Precision Results
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Tested hardware and components for high reliability
1. Active Peak Detector Operation & Diode Isolation
Passive diode-capacitor peak detectors suffer from a major flaw: the forward diode drop ($V_f approx 0.6 ext{V}$ for silicon, $0.3 ext{V}$ for Schottky) creates massive non-linear deadbands and temperature drift.
An active peak detector places the rectifying diode inside the negative feedback loop of an operational amplifier. The op-amp drives the diode with whatever voltage is necessary to equalize the voltage on the holding capacitor ($C_{hold}$) with the input signal ($V_{in}$), effectively dividing $V_f$ by the open-loop gain ($A_{OL} > 100,000$) down to mere microvolts.
2. Sizing the Holding Capacitor ($C_{hold}$)
Selecting $C_{hold}$ requires satisfying two opposing constraints:
- Acquisition Speed ($C_{hold} le C_{max}$): To capture a narrow transient pulse of duration $t_{pulse}$, the op-amp output current $I_{out}$ must charge $C_{hold}$ up to $V_{peak}$: $$C_{max} = rac{I_{out} cdot t_{pulse}}{V_{peak}}$$
- Voltage Hold Droop ($C_{hold} ge C_{min}$): During the hold phase, total leakage current $I_{total} = I_{diode_leak} + I_{buffer_bias}$ slowly drains charge off the capacitor: $$rac{dV}{dt} = rac{I_{total}}{C_{hold}} implies C_{min} = rac{I_{total} cdot t_{hold}}{Delta V_{droop_allowable}}$$
3. Dielectric Absorption (Soakage) Trap
Standard X7R/Y5V ceramic capacitors and aluminum electrolytics exhibit dielectric absorption (memory effect). Even if discharged to zero, trapped molecular dipoles slowly release residual charge, creating phantom voltages ($0.5% - 2%$ error). Precision sample-and-hold circuits strictly require low-absorption dielectrics: Polypropylene (PP), Polystyrene, Teflon (PTFE), or C0G/NP0 ceramic (dielectric absorption $< 0.02%$).
Frequently Asked Questions
Why is an ultra-low leakage diode like BAV199 recommended?
Standard 1N4148 switching diodes have reverse leakage currents of 25 nA at room temperature (and microamps at 80°C), causing rapid voltage droop in milliseconds. The BAV199 has a maximum reverse leakage of only 10 to 50 picoamps, reducing droop rate by 500x.
Why should the output buffer op-amp have a JFET or CMOS input stage?
Bipolar (BJT) op-amps draw input bias currents of 10 nA to 500 nA directly out of the holding capacitor. CMOS or JFET input op-amps (e.g. OPA140, ADA4625, TL072) draw less than 1 to 10 picoamps, ensuring long, stable hold times.
How is the peak detector reset to zero?
An N-channel JFET, low-charge-injection analog switch (e.g. ADG1201), or small MOSFET is placed in parallel across C_hold. Pulsing the gate HIGH discharges the capacitor to ground through the switch resistance (typically 5 to 100 ohms) in microseconds.
What prevents op-amp output saturation when Vin drops below Vhold?
When input drops, the diode turns off and the loop opens, driving the op-amp negative rail into saturation (phase reversal risk). Adding a secondary clamping diode from the op-amp output back to the inverting input prevents saturation and dramatically speeds up re-acquisition.