Wafer Surface Particle Deposition Calculator
Semiconductor Yield Engineering: Calculate particle deposition velocity ($v_d$), wafer surface defect accumulation, and Murphy die yield loss.
Cleanroom Air & Exposure Scenario
Defect Accumulation & Die Yield Impact
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Wafer Surface Contamination Kinetics & Semiconductor Die Yield
In advanced semiconductor manufacturing, airborne particle deposition onto polished wafer surfaces during transport and lithography causes pattern bridging, pinhole shorts, and gate dielectric breakdown.
1. Surface Deposition Rate Equation
The accumulation rate of particulate defects on a horizontal wafer surface is:
Defects = C_air · v_d · Area_wafer · Time_exposure
where $v_d$ is the combined deposition velocity ($v_g + v_{\text{diff}} + v_{\text{es}}$).
2. Murphy Die Yield Model
The relationship between surface defect density $D_0$ (defects per $\text{cm}^2$) and functional integrated circuit die yield $Y$ is modeled by Murphy's triangular probability density function:
Yield = [ ( 1 - exp(-D₀ · A_die) ) / ( D₀ · A_die ) ]²
Frequently Asked Questions
What is Deposition Velocity (v_d) and how does it determine wafer contamination?
Deposition velocity ($v_d = \dot{N}_{\text{surface}} / C_{\text{air}}$) is the empirical proportionality constant that relates the concentration of particles suspended in air to the rate at which they settle onto horizontal surfaces. It accounts for the combined effects of gravity, Brownian diffusion, and electrostatic drift.
Why does deposition velocity have a "minimum" at 0.1 to 0.2 μm?
Large particles ($d_p > 1\ \mu\text{m}$) settle quickly due to gravity (Stokes settling $v_g \propto d_p^2$). Nanoparticles ($d_p < 0.05\ \mu\text{m}$) have high Brownian diffusion coefficients ($D \propto 1/d_p$), bombarding the wafer via thermal diffusion. In the intermediate range ($0.1\text{--}0.2\ \mu\text{m}$), neither gravity nor diffusion is strong, producing a minimum deposition velocity of $\approx 10^{-4}\text{ m/s}$.
Why are Front Opening Unified Pods (FOUPs) required in modern 300 mm semiconductor fabs?
Because human personnel and cleanroom automation constantly generate particles, exposing a 300 mm wafer to ambient ISO Class 5 air for even 15 minutes adds killer defects that decimate die yield on leading-edge sub-5nm nodes. Modern fabs use airtight FOUP pods and Equipment Front End Modules (EFEM) with nitrogen purge, keeping wafers in sealed ISO Class 1 environments throughout the entire fabrication cycle.