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Power MOSFET Gate Drive & Switching Loss Physics

In high-frequency power converters (buck, boost, full-bridge inverters), MOSFET power dissipation divides into two categories: conduction loss (resistive heating when fully turned on) and switching transition loss (overlap of high voltage and high current during turn-on and turn-off transitions).

The Miller Plateau & Switching Times

During turn-on, the gate voltage charges until it reaches the Miller Plateau ($V_{pl}$), where the gate voltage flatlines while all incoming gate current is absorbed by discharging the reverse transfer capacitance ($C_{rss} / Q_{gd}$). The duration of this transition governs the $V_{DS}$ fall time: $$I_{gate,on} = \frac{V_{DRV} - V_{pl}}{R_{loop}}, \quad t_r \approx \frac{Q_{gd}}{I_{gate,on}}$$ Similarly, during turn-off: $$I_{gate,off} = \frac{V_{pl}}{R_{loop}}, \quad t_f \approx \frac{Q_{gd}}{I_{gate,off}}$$ Where $R_{loop} = R_{drv} + R_G + R_{g,int}$.

Switching Loss vs. EMI Ringing Tradeoff

• Smaller $R_G$: Accelerates $t_r$ and $t_f$, dramatically reducing switching losses, but increases $di/dt$ and $dv/dt$, provoking high-frequency ringing on parasitic trace inductances ($L_{trace}$) and high EMI.
• Larger $R_G$: Suppresses ringing and softens switching edges, but prolongs transition times and increases switching heat dissipation ($P_{sw} = \frac{1}{2} V_{DS} I_D (t_r + t_f) f_{sw}$).