Photolithography Overlay Error Budget Calculator

Semiconductor scanner metrology & yields: Decompose and calculate layer-to-layer overlay budgets ($3sigma_{overlay}$), stage alignment tolerances, reticle errors, and wafer thermal expansion.

Scanner Stage & Reticle Error Components

Wafer Stage Grid Error σ_stage (nm): Interferometer stage positioning 1σ

Alignment Metrology Noise σ_align (nm): Mark sensor contrast & repeatability

Reticle Writing / Mag Error σ_reticle (nm): Mask registration on-wafer equivalent

Lens Aberration / Distortion σ_lens (nm): Intra-field optical lens heating & distortion

Wafer Thermal Drift ΔT (mK): Temperature gradient across 300mm wafer

Target Critical Dimension CD (nm): Critical dimension for overlay rule

Total Overlay Error & Node Budget

Total 3-Sigma Overlay (3σ_tot)

Overlay Budget Limit (20% CD)

Thermal Expansion Offset (ΔR)

R_wafer · α_Si · ΔT

Dominant Contributor

Primary variance source

Edge-Die Overlay Risk

At 150 mm radius

Dedicated Metrology Target

DBO / AIM grating in scribe lane

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Frequently Asked Questions

What is the difference between overlay and critical dimension (CD)?

Critical dimension (CD) is the measured width or size of a printed feature (e.g. a 16 nm wire). Overlay is the positional offset or displacement between two different pattern layers relative to each other (e.g. a via landing off-center on a wire).

What is Diffraction-Based Overlay (DBO)?

DBO measures overlay using periodic diffraction grating targets placed in wafer scribe alleys. Optical sensors measure asymmetry in the +1 and -1 diffraction orders, providing sub-nanometer overlay accuracy without imaging sensor resolution limits.

Why does wafer heating occur during EUV exposure?

EUV radiation carries high photon energy (91.8 eV). Because exposure takes place in vacuum where convective air cooling cannot occur, absorbed EUV power heats the wafer chuck, causing local thermal distortion that must be actively compensated by water-cooled chucks.