Free PLL Charge Pump & Loop Filter Tool
Calculate passive 2nd & 3rd order loop filter components ($C_1, R_2, C_2, R_3, C_3$) for integer-N and fractional-N PLL frequency synthesizers to optimize lock time & phase noise.
⚡ PLL Architecture & Dynamics
📊 Filter Component Values & Response
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1. Role of the Loop Filter in Phase-Locked Loops
In a charge pump PLL (such as Analog Devices ADF4351 or Texas Instruments LMX2594), the Phase-Frequency Detector (PFD) outputs current pulses proportional to phase error between reference $f_{comp}$ and divided VCO feedback $f_{out}/N$.
The loop filter converts these current pulses into a smooth DC tuning voltage ($V_{tune}$) to steer the Voltage-Controlled Oscillator (VCO). Sizing the loop filter governs the fundamental trade-off of synthesizer design:
- Wide Bandwidth ($f_c$): Accelerates lock acquisition time and suppresses close-in VCO phase noise, but allows reference spur leakage and charge pump noise.
- Narrow Bandwidth ($f_c$): Provides exceptional reference spur rejection and filters out reference clock noise, but slows lock times and allows free-running VCO phase noise to dominate.
2. Passive 2nd and 3rd Order Filter Architecture
The standard passive 2nd order filter consists of:
- Series $R_2$ and $C_2$: Creates an integration pole at the origin plus a stabilizing zero ($omega_z = 1 / R_2 C_2$) that introduces phase lead, establishing the desired phase margin ($phi_m approx 45^circ - 60^circ$).
- Parallel $C_1$: Shunts discrete charge pump ripple pulses to ground, creating a high-frequency pole ($omega_{p1} = 1 / R_2 C_{parallel}$).
- Additional $R_3$ and $C_3$ (3rd Order): Adds a secondary pole at approximately $3 imes$ to $5 imes$ loop bandwidth, adding an extra $20 ext{ dB}$ of reference spur suppression without eroding phase margin.
3. Gardner's Stability Limit ($f_c le f_{comp} / 10$)
Continuous-time Laplace approximations break down if loop crossover bandwidth exceeds $1/10$ of the discrete comparison sampling frequency: $$f_c le rac{f_{comp}}{10}$$ Violating this limit causes discrete sampling instability, severe phase jitter, and transient cycle slipping.
Frequently Asked Questions
Why is phase margin chosen between 45 and 60 degrees?
A phase margin of 48° to 50° delivers the fastest settling time with minimal ringing. Margins below 40° cause severe underdamped transient overshoot. Margins above 65° become sluggish and overdamped.
What type of capacitors should be used in a PLL loop filter?
Use C0G/NP0 ceramic capacitors for values up to 1 nF, and Polyphenylene Sulfide (PPS) or Polypropylene film capacitors for larger values. Never use standard X7R/X5R ceramics in the loop filter, as piezoelectric microphonics will modulate the VCO tuning line and create audio spurs.
How does VCO gain (Kvco) affect the loop filter?
Loop gain is directly proportional to Kvco * I_cp. If Kvco varies widely across the tuning range (e.g. 20 MHz/V at 1V up to 60 MHz/V at 4V), the loop bandwidth will also vary. Designers select I_cp settings via register software to keep the Kvco * I_cp product constant.
What is the lock time of a charge pump PLL?
Settling time to within a narrow frequency tolerance is approximately 4 to 5 time constants: t_lock ≈ 4 / f_c. For a 100 kHz loop bandwidth, lock time is roughly 40 microseconds.