Wafer Thermal Stress Slip Calculator
Semiconductor Furnace & RTP Processing: Model radial thermal gradients, maximum hoop stresses, resolved shear stress on {111}⟨110⟩ slip systems, and slip line risk.
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Thermal Stress & Dislocation Slip Criterion
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Wafer Thermal Stress & Alexander-Haasen Dislocation Model
Managing radial temperature uniformity in vertical diffusion furnaces and single-wafer Rapid Thermal Processing (RTP) chambers is critical for defect-free 300 mm and 450 mm semiconductor manufacturing.
1. Radial Thermal Hoop Stress
For a parabolic radial temperature distribution $T(r) = T_0 + \Delta T_r (r/R)^2$, maximum tensile hoop stress develops at the wafer edge:
σ_θ(R) = 0.5 · α(T) · E(T) · ΔT_r
Nucleation occurs whenever the resolved shear stress $\tau_{rss} = S_0 \cdot \sigma_\theta(R)$ exceeds the critical resolved shear stress $\tau_{crss}(T)$.
Frequently Asked Questions
What causes slip dislocation lines in silicon wafers during thermal processing?
When wafers heat up or cool down rapidly in diffusion furnaces or RTP chambers, radiative heat loss from wafer perimeters creates large radial temperature differences (ΔT_r) between wafer centers and edges. The resulting hoop thermal stress, resolved onto {111} planes along ⟨110⟩ slip directions, exceeds the temperature-dependent critical resolved shear stress (CRSS) of silicon, generating macroscopic slip dislocation arrays.
Why does silicon yield strength drop drastically at elevated temperatures?
At room temperature, silicon is completely brittle because covalent Si-Si bonds resist dislocation glide. Above its brittle-to-ductile transition (~600°C), thermally activated dislocation kink nucleation and glide become effortless, causing CRSS to plummet exponentially from gigapascals to single-digit megapascals at 1000°C–1200°C.
What are the catastrophic effects of slip lines on semiconductor integrated circuits?
Slip lines introduce dense atomic dislocation lines that penetrate transistor active areas. These defects act as high-speed diffusion pipes for metal contaminants, causing severe gate oxide breakdown, p-n junction leakage currents, and non-uniform chemical mechanical planarization (CMP).