Through-Silicon Via TSV Delay Calculator
3D IC & Heterogeneous Packaging: Determine electrical resistance ($R$), liner/depletion capacitance ($C$), RC propagation delay ($\tau_{50}$), and cutoff frequency for copper Through-Silicon Vias.
TSV Physical Dimensions & Aspect Ratio
Substrate & Driver Loading
TSV Impedance & Propagation Delay
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Through-Silicon Via (TSV) Interconnect Electrical Modeling
In 3D IC architectures and High-Bandwidth Memory (HBM), through-silicon vias provide dense, short vertical interconnects across stacked silicon dies.
1. Coaxial Liner Capacitance & Resistance
R_tsv = ρ_Cu · [ H_tsv / (π · r_tsv²) ] C_ox = [ 2π · ε_0 · κ_ox · H_tsv ] / ln( (r_tsv + t_ox) / r_tsv )
2. Elmore Propagation Delay
The 50% signal propagation delay through a loaded TSV stage:
τ_50 = 0.693 · [ R_dr · (C_tsv + C_load) + R_tsv · (0.5·C_tsv + C_load) ]
Frequently Asked Questions
What is a Through-Silicon Via (TSV) and why is it essential for 3D ICs?
A Through-Silicon Via (TSV) is a microscopic vertical electrical conduit etched completely through a thinned silicon wafer or die and filled with electroplated copper. Unlike wire bonding along die peripheries, TSVs route signals vertically through the active silicon, shortening interconnect lengths by $100\times$ to $1000\times$ and enabling ultra-high bandwidth in 3D memory stacks (HBM) and heterogeneous compute chiplets.
What limits the aspect ratio (AR) of a TSV in high-volume manufacturing?
TSV aspect ratio ($AR = H / D$) is restricted by deep reactive ion etching (Bosch DRIE) rate drop and electroplating void formation. At aspect ratios exceeding $10:1$ or $12:1$, conformal deposition of physical vapor deposition (PVD) barrier/seed layers and void-free bottom-up copper fill becomes difficult, risking high electrical resistance or early electromigration voiding.
How does the dielectric liner oxide affect TSV parasitic capacitance?
The thin silicon dioxide ($SiO_2$) or silicon nitride liner insulates the copper core from the semi-conductive bulk silicon. Because the liner forms a cylindrical capacitor, thinner oxides reduce manufacturing cost but increase parasitic capacitance ($C_{ox} \propto 1 / \ln(1 + t_{ox}/r)$), which increases dynamic switching power ($P = C V^2 f$) and signal propagation delay.