Free CAN Bus Bit Timing & Delay Tool
Configure CAN controller bit timing registers ($BRP, Prop\_Seg, Phase\_Seg1, Phase\_Seg2$), target sample points ($75\% - 87.5\%$), and maximum cable length without bus arbitration failure.
🚗 CAN Controller Clock & Baud Rate
📊 Register Configuration & Cable Limits
Recommended Tools & Equipment
Tested hardware and components for high reliability
The Mechanics of CAN Bus Bit Timing and Propagation Delay
Controller Area Network (CAN) utilizes bit-by-bit non-destructive arbitration based on dominant (logic 0) and recessive (logic 1) states. For arbitration to work across a distributed bus, a dominant bit transmitted by any node must propagate to the farthest node and return before the transmitter samples the bit. This physical constraint dictates Nominal Bit Timing.
CAN Bit Time Segments (ISO 11898)
A single bit period is divided into four non-overlapping segments totaling (N_{Tq}) Time Quanta:
- Sync_Seg: Fixed at (1 T_q). Used to synchronize nodes on edges.
- Prop_Seg: Compensates for physical delays along the bus cable, transceivers, and optocouplers.
- Phase_Seg1: Phase buffer segment before the sample point.
- Phase_Seg2: Phase buffer segment after the sample point.
The Sample Point is the moment the controller reads the bus level:
$$ ext{Sample Point } % = rac{ ext{Sync_Seg} + ext{Prop_Seg} + ext{Phase_Seg1}}{N_{Tq}} imes 100%$$
Propagation Delay & Cable Length Limits
The total round-trip propagation delay is: (t_{round} = 2 cdot (t_{transceiver} + t_{cable} cdot L)). For arbitration to succeed without false bit errors, the hardware constraint requires:
$$t_{round} le ( ext{Prop_Seg} + ext{Phase_Seg1}) cdot T_q$$
Frequently Asked Questions
Why does a 1 Mbps CAN bus have a 25 to 40 meter maximum cable limit?
At 1 Mbps, the entire bit period is only 1000 ns. Round-trip transceiver delay consumes ~300 ns, leaving only ~400 ns for cable transit. At 5 ns/meter, 400 ns corresponds to an 80m round-trip or 40m maximum cable length.
What is Synchronization Jump Width (SJW)?
SJW defines the maximum number of Time Quanta by which Phase_Seg1 can be lengthened or Phase_Seg2 shortened to compensate for clock drift between crystal oscillators. It is typically configured to min(Phase_Seg1, 4).