Synchronous Buck Bootstrap Circuit Calculator
Size bootstrap capacitors, damping resistors, and calculate minimum low-side refresh times and maximum duty cycle limits to prevent high-side gate UVLO dropout.
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Synchronous Buck Bootstrap Gate Drive Sizing Fundamentals
In high-efficiency synchronous buck converters and half-bridge inverters, both high-side and low-side switches are N-channel MOSFETs. Driving the high-side N-FET into full saturation requires elevating its gate voltage 10V above the floating switch node ((V_{SW})). This is achieved using a flying bootstrap capacitor ((C_{\text{boot}})) and bootstrap diode.
1. Bootstrap Capacitance Minimum Sizing Formula
During the high-side ON-time (t_{\text{on}}), the bootstrap capacitor must supply all gate charge (Q_g), driver quiescent current (I_{qbs}), and level-shifter charge (Q_{ls}) without drooping by more than (\Delta V_{\text{boot}}):
$$Q_{\text{total}} = Q_g + I_{qbs} \cdot t_{\text{on}} + Q_{ls}$$
$$C_{\text{boot(min)}} = \frac{Q_{\text{total}}}{\Delta V_{\text{boot}}}$$
Best engineering practice dictates using a ceramic capacitor ((X7R)) with an actual effective capacitance equal to at least 10 to 15 times the MOSFET equivalent input capacitance to ensure minimal voltage droop.
2. Why Series Resistor (R_{\text{boot}}) is Essential
When the low-side switch turns ON, the switch node plunges to ground, recharging (C_{\text{boot}}). Without a series resistor (R_{\text{boot}}) (typically 2.2Ω to 5.1Ω), the instantaneous inrush current can exceed 10A, causing high-frequency ringing and driving the switch node negative ((V_{SW} < -2\text{V})), which can induce parasitic latch-up in the gate driver IC.
3. Low-Side Refresh Time & 100% Duty Cycle Limits
Because (C_{\text{boot}}) recharges exclusively when the switch node is pulled low, a pure bootstrap driver cannot operate at 100% continuous duty cycle. The low-side MOSFET must remain ON for at least 3 time constants ((t_{\text{refresh}} \ge 3 \cdot R_{\text{boot}} C_{\text{boot}})) each switching cycle to replenish depleted charge.
Frequently Asked Questions
What causes bootstrap undervoltage lockout (UVLO) trip during step-load transients?
When the control loop commands a long burst of high duty cycle pulses to respond to a sudden load step, the low-side ON-time shrinks below the time needed to recharge Cboot. The capacitor voltage droops below the UVLO threshold, causing the gate driver to shut down.
Can I use an electrolytic or tantalum capacitor for Cboot?
No. Electrolytic and tantalum capacitors have high equivalent series resistance (ESR) and equivalent series inductance (ESL), which cannot deliver the multi-ampere nanosecond current pulses required to charge the MOSFET gate. Always use low-ESR surface-mount ceramic capacitors (X7R or X8R).