PDN Target Impedance & Decoupling Capacitor Array Calculator
Calculate Power Distribution Network (PDN) target impedance (Ztarget), maximum allowable transient voltage ripple, bulk capacitor reservoir requirements, and high-frequency MLCC ceramic decoupling capacitor array sizing up to knee frequency.
Supply Rail & Transient Dynamics
V
Core rail voltage (e.g. 0.85V-1.8V for FPGAs/SoCs).
%
Maximum permitted voltage deviation (typically ±2% to ±5%).
A
Dynamic load step from low-power to active processing.
ns
Clock switching slew time (sets knee frequency).
µs
Power supply control loop feedback delay.
Target PDN Impedance & Array
SUB-MILLIOHM
Target Impedance (Ztarget)
3.00 mΩ
Max ripple: ±30.0 mV
Knee Frequency (fknee)
350 MHz
Upper bandwidth of transient
Minimum Bulk Capacitance
3,333 µF
Sustains rail during VRM delay
Recommended MLCC Count
18 × 100nF
Keeps ESL array below target
Capacitor Array Paralleling Strategy
Anti-Resonance Safe
Bulk Storage Requirement:
8 × 470µF Polymer Tant
Array Effective ESL:
27.8 pH
Array Resonant Freq (SRF):
22.5 MHz
Multiple identical MLCCs in parallel suppress anti-resonant peaks and distribute high-frequency current evenly around IC power pins.
Istvan Novak / Bogatin PDN Equations:
• Allowable Ripple: (Delta V = V_{ ext{dd}} cdot ( ext{Ripple%} / 100))
• Target Impedance: (Z_{ ext{target}} = rac{Delta V}{Delta I})
• Bulk Sizing: (C_{ ext{bulk}} = rac{Delta I cdot t_{ ext{VRM}}}{Delta V}), Knee Freq: (f_{ ext{knee}} = rac{0.35}{t_r})