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Free Charge Pump Switched-Capacitor Calculator Electronics & Embedded
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Free Charge Pump Switched-Capacitor Calculator

Calculate output resistance (Rout), flying capacitor (Cfly) requirements, slow & fast switching limits, and voltage ripple for switched-capacitor inverters and doublers.

Charge Pump Configuration

V
mA
µF
Pump transfer capacitor
µF
Output filter capacitor
kHz
ICL7660 = 10k, BOOST = 40k
Ω
MOSFET switch resistance

📊 Impedance & Output Performance

Loaded Output Voltage (Vout)
-4.25 V
Voltage Drop: 0.75 V (15.0% sag under 25 mA load)
Total Output Resistance (Rout)
30.0 Ω
SSL: 10.0Ω | FSL: 20.0Ω
Output Peak-to-Peak Ripple
125 mV_pp
ΔV = Iload / (2 * f * Cout)
Dominant Impedance Limit
Fast Switching (FSL)
Limited by switch R_on
Power Efficiency (η)
85.0%
P_out / P_in
💡 How to Cut Charge Pump Rout in Half
If your charge pump is operating in the Slow Switching Limit (SSL), increasing C_fly from 10 µF to 47 µF dramatically lowers Rout. If in the Fast Switching Limit (FSL), capacitor size no longer matters; you must tie the BOOST pin high or upgrade to a lower R_on IC (like MAX660 / 6.5Ω).

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How Switched-Capacitor Charge Pumps Work

Switched-capacitor charge pumps generate a negative or multiplied rail (such as generating -5V from +5V for analog op-amps) using only switches and capacitors—completely eliminating bulky inductors and magnetic EMI radiation.

1. The Two Asymptotic Impedance Limits

The output impedance ($R_{out}$) of an unregulated charge pump governs how much output voltage sags under load:

  • Slow Switching Limit (SSL): At low switching frequencies, the flying capacitor has plenty of time to fully charge and discharge during each clock phase. Impedance is purely capacitive:
    R_SSL = 1 / [f_sw × C_fly]
  • Fast Switching Limit (FSL): At high switching frequencies, the capacitor cannot fully charge because internal MOSFET switch resistance ($R_{on}$) and capacitor Equivalent Series Resistance (ESR) bottleneck the current:
    R_FSL ≈ 4 × R_on + 2 × ESR_fly

The total equivalent output resistance is approximately the sum: $R_{out} approx R_{SSL} + R_{FSL}$.

2. Peak-to-Peak Voltage Ripple

During the discharge phase, the output reservoir capacitor ($C_{out}$) sustains the entire load current for half a cycle ($T / 2$):

ΔV_ripple = I_load / [2 × f_sw × C_out] + (I_load × ESR_out)

Using multi-layer ceramic capacitors (MLCC) with sub-10 mΩ ESR virtually eliminates the resistive ripple component.

Frequently Asked Questions

Why does my ICL7660 whine audibly in audio circuits?

The classic ICL7660 oscillates at ~10 kHz, directly in the middle of human hearing. When current pulses flow through ceramic capacitors, piezoelectric acoustic noise creates an audible 10 kHz whine. Tying pin 1 (BOOST) to V+ shifts the oscillator frequency to ~40-45 kHz, moving it well above the human hearing range.

Can I parallel two charge pumps for higher current?

Yes! Connecting two charge pump ICs in parallel with synchronized or separate clocks halves the effective output resistance (Rout_total = Rout / 2), doubling the safe output current capability.

Why do charge pump capacitors require low ESR?

Charge pumps transfer charge in high-amplitude instantaneous current spikes. High ESR electrolytic capacitors cause severe thermal heating, inflate Rout, and introduce excessive high-frequency voltage spikes onto sensitive analog rails. Always use X7R or X5R ceramic capacitors.

What is the maximum voltage I can feed into an ICL7660?

Standard ICL7660 and MAX1044 ICs have an absolute maximum rating of 10.0V (some economy variants only 5.5V). Exceeding this rating causes internal SCR latch-up. For 12V or 15V systems, you must use high-voltage variants such as the ICL7660A or TC7662A (rated up to 18V).